A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance C=εεo A/d, where ε is the dielectric constant of the capacitor dielectric, εo is the vacuum permittivity, A is the electrode (or storage node) area, and d is the interelectrode spacing. The conditions of DRAM operation, such as operating voltage, leakage rate and refresh rate, will in general mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each must maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Nevertheless, in the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. For example, the area allowed for a single cell in a 64-Mbit DRAM is only about 1.4 μm2. In such limited areas, it is difficult to provide sufficient capacitance using conventional stacked capacitor structures. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area.
Several techniques have been developed to increase the total charge capacity or the capacitance of the cell capacitor without significantly affecting the cell area.
For example, new capacitor dielectric materials with high dielectric constants have been introduced to replace conventional dielectric materials such as silicon nitride. This way, thin films of materials having a high dielectric constant, such as Ta2O5 (tantalum pentoxide), Barium Titanate (BT), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), or Bismuth Strontium Titanate (BST), have been increasingly utilized as the cell dielectric material of choice of DRAMs. Although these materials have a high dielectric constant and low leakage currents, there are some technical difficulties associated with these materials.
One problem with incorporating these materials into current DRAM cell designs is their chemical reactivity with the polycrystalline silicon (polysilicon or “poly”) that conventionally forms a capacitor electrode of a metal-insulator-semiconductor (MIS) capacitor. Capacitors made of polysilicon-PZT/BST sandwiches undergo chemical and physical degradation with thermal processing. During the chemical vapor deposition (CVD) of PZT/BST, oxygen in the ambient tends to oxidize the electrode material. The oxide is undesirable because it has a much lower dielectric constant compared to that of PZT/BST, and adds in series to the capacitance of the PZT/BST, thus drastically lowering the total capacitance of the capacitor. Thus, even a thin native oxide layer present on the electrode results in a large degradation in capacitance.
Accordingly, there is a need for a method of forming a metal-insulator-semiconductor (MIS) capacitor having increased capacitance per cell and low leakage, as well as a method of forming a capacitor structure that achieves high storage capacitance without increasing the size of the capacitor. An MIS capacitor with increased capacitance and reduced leakage current is also needed.